The present invention relates to integrated circuit development, and more specifically, to the superposition of canonical timing value representations in statistical static timing analysis (SSTA).
The development of an integrated circuit involves many phases from developing a high-level logic design to fabricating a final design into the physical implementation of the integrated circuit (i.e., chip). An electronic design automation (EDA) tool can be used to perform many of the processes such as logic synthesis and physical synthesis. In addition to ensuring that the chip logic performs the desired functions, tests and processes throughout the development also ensure that timing and power requirements of the chip are met. Thus, timing analysis is performed at different phases and can be performed iteratively.